集成电路形式化验证的理论与应用
日期：2024/08/06 - 2024/08/06
学术讲座：集成电路形式化验证的理论与应用
主讲人：Dr. You Li, Postdoctoral Scholar at Northwestern University
时间：2024年8月6日（周二）上午9:00-10:00
地点：Online, Feishu: vc.feishu.cn/j/246082986
讲座摘要
Verification is conducted throughout the entire VLSI design and manufacturing flow. It reduces the risk of costly rework and tapeout failures by ensuring that the chip design always meets its specification. Formal verification is a prominent technique in VLSI verification, offering benefits such as exhaustiveness, mathematical rigor, and explainability. This talk will explore ways to enhance the scalability and usability of formal methods for both functional and security verification. Topics include formal equivalence checking for sequential design transformations, real-time configuration verification for network systems, and formal security analysis for logic encryption. The talk will also discuss future directions, such as applying formal verification to mitigate hallucinations in LLM-generated designs and leveraging hardware root-of-trust to enhance the security of AI applications.
主讲人简介
You Li is currently a postdoctoral scholar at Northwestern University. He obtained his Ph.D. degree in computer engineering from Northwestern University, advised by Prof. Hai Zhou. He received his Bachelor's degree from the University of Michigan - Shanghai Jiao Tong University Joint Institute. His research interests include formal verification and hardware security.