Circuit and Algorithm Design for Edge Intelligence

Date: 2020/12/16 - 2020/12/16

Academic Seminar: Circuit and Algorithm Design for Edge Intelligence

Speaker: Ningyuan Cao

Time: 9:00 a.m.-10:00 a.m., December 16th, 2020 ( Beijing Time)

Location: via Zoom (Meeting ID: 64626518851, Password: 9972)


This presentation will highlight circuit and algorithm innovations of edge intelligence (EI) to provide a comprehensive insight into EI design/research challenges and opportunities. The convergence of Internet of Things (IoT) and Artificial Intelligence (AI) is fundamentally reshaping our interactions with the world. In the new relationship, enhanced capabilities in perceiving, analyzing and reacting to the world are empowered through expanded IoT network, augmented data dimension and escalated AI complexity. However, state-of-art cloud based-IoT framework, due to its intrinsic shortcomings rooted in its centralized architecture, can lead to numerous issues with respect to privacy, latency, robustness, local-awareness and so on. EI provides such a de-centralized scheme that offloads information inference ability to the end nodes that seamlessly connect world to the human society. However, it still remains a question of how to bridge the technology gap between reality and our expectations to next-generation intelligence on resource-constrained edge devices. In this presentation, the speaker will give brief introductions to EI, its research opportunities and a generic EI design methodology. Further, the speaker will present recent research advances in swarm robotic computational ASIC, fully-on-chip wireless image IoT SOC and hardware-inspired sparse-neural-network processor as examples to illustrate proposed EI design methodology. Finally, future EI research fields will be discussed to provide a vision into what are emerging technologies that could propel EI further with the development of smart society.


Ningyuan Cao received his B.S. degree in Electrical Engineering from Shanghai Jiaotong University, Shanghai, China, in 2013. In 2015, he received his M.S. degree in Electrical Engineering from the Columbia University, New York, USA. From June, 2014 to May, 2015, he was a staff research associate at Columbia Integrated Circuit Laboratory (CISL), Columbia University, New York, USA. Since September 2015, he has been pursuing his Ph.D. degree in School of Electrical and Computer Engineering at the Georgia Institute of Technology, and received his doctorate degree in August 2020. He is currently working as postdoctoral research fellow for IBM T.J. Watson research center and ICSRL of Georgia Institute of Technology. His research interests cover various disciplines, including low-power machine learning ASIC design, wireless sensor SOC design and circuit design automation. These interests are directed towards the mutual enhancement between AI hardware and machine learning circuit design automation. His research has so far resulted in numerous top-tier IEEE journals/conference publications, including ISSCC, JSSC, TIE, ISCAS, TCAS-I, IMS, SENSORS and so on. Going forward, he will continue his exploration in the fields to enable next-generation edge intelligence, including brain-inspired edge computation, hardware security, RF machine learning systems and so on.