Chip Design in the 21st Century: The Intersection of Everything
Date: 2022/05/27 - 2022/05/27
Academic Seminar: Chip Design in the 21st Century: The Intersection of Everything
Speaker: Xinfei Guo, Assistant Professor, UM-SJTU Joint Institute, Shanghai Jiao Tong University
Time: 10:00 a.m.-11:30 a.m., May 27th, 2022 (Beijing Time)
Location: via Feishu, https://vc.feishu.cn/j/956639818
Semiconductors have been described as the ‘new oil’ of the 21st century. They underpin every facet of technology and the unassuming computer chip has become a treasure for massive computing. With the increasing complexity of semiconductor chips (with billions of transistors), movement towards “end of Moore’s law”, tighter time-to-market requirements, booming AI and ML industry and changes in the Electronic Design Automation (EDA) tools in the 21st century, semiconductor industry is facing unprecedented challenges at all levels – nanomaterials, technology process node, circuits and microarchitectures, packaging, design methodology and EDA tools. On the chip design front, the challenges came from the question on how to find the best design point out of a growing design space that is set by very specific applications. As a result, we see 1.2-trillion transistor wafer-scale chips that are used for AI training today, and we also see 1-million transistor microprocessor chips that are deployed on the edge. Designing these chips needs to understand the physics to deal with the tiny leakage power at the single transistor level, and it also requires the best algorithms to place all the cells on a large floorplan “canvas”. It is a necessity rather than a choice for everything to intersect when designing a chip in the 21st century. In this talk, I will briefly go over the reasoning, history and facts behinds some of these evolutions. In the end of talk, I will also share my views on how to design a high-quality modern chip through a cross-layer approach.
Xinfei Guo is a tenure-track assistant professor at JI. He is also a senior member of IEEE. He received his PhD in Computer Engineering from the University of Virginia. He also holds a Master’s degree in Electrical and Computer Engineering from the University of Florida. Before joining JI, he worked at Nvidia and IBM research in US, where he served as a key member to contribute to multiple chip products, including the world-leading BlueField Data Processing Units (DPU) and a total of 7 chip tapeouts that cover a wide range of technology nodes from 180nm to 7nm. His previous work has results in over 30 conference or journal papers in IC design, EDA or FPGA fields. He also published a book. His current research interests include low power and reliable computing, machine learning-assisted design automation techniques and reconfigurable computing.