Formal Verification in VLSI Design Automation: From Theoretical Foundations to Practical Applications

Date: 2024/08/06 - 2024/08/06

Academic Seminar: Formal Verification in VLSI Design Automation: From Theoretical Foundations to Practical Applications

Speaker: Dr. You Li, Postdoctoral Scholar at Northwestern University

Time: 9:00-10:00 a.m., August 6, 2024 (Beijing Time)

Location: Online, Feishu: vc.feishu.cn/j/246082986

Abstract

Verification is conducted throughout the entire VLSI design and manufacturing flow. It reduces the risk of costly rework and tapeout failures by ensuring that the chip design always meets its specification. Formal verification is a prominent technique in VLSI verification, offering benefits such as exhaustiveness, mathematical rigor, and explainability. This talk will explore ways to enhance the scalability and usability of formal methods for both functional and security verification. Topics include formal equivalence checking for sequential design transformations, real-time configuration verification for network systems, and formal security analysis for logic encryption. The talk will also discuss future directions, such as applying formal verification to mitigate hallucinations in LLM-generated designs and leveraging hardware root-of-trust to enhance the security of AI applications.

Biography

You Li is currently a postdoctoral scholar at Northwestern University. He obtained his Ph.D. degree in computer engineering from Northwestern University, advised by Prof. Hai Zhou. He received his Bachelor's degree from the University of Michigan - Shanghai Jiao Tong University Joint Institute. His research interests include formal verification and hardware security.