In-memory Compute with Off-the-shelf DRAM (Virtual)

Date: 2023/08/24 - 2023/08/24

Academic Seminar: In-memory Compute with Off-the-shelf DRAM (Virtual)

Speaker: Fei Gao, Princeton University

Time: 10:00 a.m., August 24, 2023 (Beijing Time)

Location: Room 403, JI Long Bin Building /Feishu ID: 675201371


In-memory computing has long been promised as a solution to the “Memory Wall” problem. Unfortunately, performing computations with memory resources either has relied on emerging memory technologies which are not readily available today or has required additional circuits be added to RAM arrays. So far, the competitive and low-margin nature of the RAM industry has made commercial RAM manufacturers resist adding any additional logic into the existing design. In this talk, we demonstrate methods of in-memory compute with off-the-shelf DRAM chips without any hardware modification, thus make it more realistic and ready-to-use.

We found that specially timed DRAM command sequences lead to undocumented, but also constructive and stable behaviors in DRAM array. We studied and characterized those behaviors with a customized DRAM controller and unmodified DRAM modules from major DRAM vendors. We propose a DRAM command sequence that can open multiple DRAM rows at the same time, thereby enabling bit-line charge sharing. With the charge sharing, we implement intra-subarray row copy and majority-of-three operations. Subsequently, these primitive operations are employed to develop an architecture for arbitrary, massively-parallel, bit-serial computation with off-the-shelf DRAM. Subsequently, additional command sequences are proposed to store fractional value in a DRAM cell. Utilizing fractional value storage, we could enable more modules to perform the in-memory majority operation, increase the stability of the existing in-memory majority operation, and build a state-of-the-art DRAM-based PUF with unmodified DRAM.


Fei Gao received his B.Eng. degree in microelectronics from Tsinghua University, Beijing, in 2017, and his M.A. degree in electrical engineering from Princeton University, New Jersey, in 2019, where he is currently pursuing his Ph.D. degree. His research focuses on in-memory computing and manycore heterogeneous architecture.